A conventional field effect transistor (FET), also known as a metal oxide semiconductor (MOS) transistor, generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of carriers in the channel. Thus the higher the mobility of the carriers in the channel, the more current can flow and the faster a circuit can perform. One way to increase the mobility of the carriers in the channel of an MOS transistor is to produce a mechanical stress in the channel.
A compressive strained channel, such as a silicon-germanium channel layer grown on silicon, has significant hole mobility enhancement. A tensile strained channel, such as a thin silicon channel layer grown on relaxed silicon-germanium, achieves significant electron mobility enhancement. The most common method of introducing tensile strain in a silicon channel region is to epitaxially grow the silicon channel layer on a relaxed silicon-germanium (SiGe), layer or substrate. The ability to form a relaxed SiGe layer is important in obtaining an overlying, epitaxially grown, silicon layer under biaxial tensile strain, however the attainment of the relaxed SiGe layer can be costly and difficult to achieve.
Another method of obtaining a tensile strain in the channel is to epitaxially grow a SiC layer over the entire active area. A disadvantage of this method is that carbon within the channel portion of the strain layer can migrate into the overlying gate oxide, thereby causing a relatively large interface trap density (DIT), which disadvantageously increases scattering and reduces the mobility advantages associated with the strained channel. Another important issue with this approach is the problem of getting the C atoms in substitutional lattice site in silicon. For the strain to manifest, the C atoms should be in substitutional sites.
Many different source and drain doping methodologies and profiles have been used to modify the operating characteristics of FETs. Lightly- and mildly-doped drain regions (LDD and MDD, respectively) and extensions have been used to adjust the structure and operation of an FET. Pocket dopant implantations proximate the channel regions have similarly been used to affect device structure and operation. Buried regions, different types of dopant implantation processes and materials, different annealing process parameters and other well-known process and material variations have all been used with varying degrees of success to adjust the operating characteristics of FETs. It is believed that these P- and N-type dopants affect the semiconductor properties of the silicon by affecting the mobility and flow of electrons within the silicon crystal lattice structure.
It would be advantageous to have a transistor device and method that effectively and reliably provides strain to the device in order to improve carrier mobility.